AK4452VN Datasheet, PDF (30/91 Pages) Asahi Kasei Microsystems – 115dB 768kHz 32-bit 2ch Premium DAC

[AK4452]
9. Functional Descriptions
■ D/A Conversion Mode
The AK4452 can perform D/A conversion for either PCM data or DSD data. The DP bit controls PCM/DSD
mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode, PCM
data can be input from BICK, LRCK and SDTI pins. When PCM/DSD mode is changed by DP bit, the
AK4452 should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. Only a PCM data is
supported in parallel mode.
DP bit Interface
0
PCM
1
DSD
Table 1. PCM/DSD Mode Control
■ System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4452, are MCLK, BICK and LRCK. MCLK should
be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta - sigma modulator.
There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit= “0”: Default), the
sampling speed is set by DFS0, DFS1 (Table 2). The frequency of MCLK at each sampling speed is set
automatically. When reset is released (PDN pin = “↑”), the AK4452 is in Manual Setting Mode. In Auto
Setting Mode (ACKS bit= “1”), as MCLK frequency is detected automatically (Table 5) and the internal
master clock attains the appropriate frequency (Table 6, Table 7), so it is not necessary to set DFS bits. When
changing the clock, the AK4452 must be reset by the PDN pin or RSTN bit.
Rev. 0.1
- 30 -
2014/04