AK4452VN Datasheet, PDF (63/91 Pages) Asahi Kasei Microsystems – 115dB 768kHz 32-bit 2ch Premium DAC

[AK4452]
■ Power Down Function
The AK4452 is placed in power-down mode by bringing the PDN pin “L” and the analog outputs become
floating (Hi-Z) state. Power-up and power-down timings are shown in Figure 61.
Power
PDN pin
(1)
VDD18 pin
Internal PDN
Internal
State
(2)
Normal Operation (register write and DAC input are available)
Reset
DAC In
(Digital)
DAC Out
(Analog)
(4)
(5)
Clock In
Don’t care
MCLK,LRCK,BICK
“0”data
(3)
GD
“0”data
GD
(5)
(4)
(6)
Don’t care
DZF
(8)
External
Mute
(7)
Mute ON
Mute ON
Notes:
(1) After AVDD and TVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) After PDN pin = “H”, the internal LDO power-up if the LDOE pin = “H”. The internal circuits will be
powered up after shutdown switch is ON in the end of a counter by the internal oscillator
(10ms(max)).
If the LDOE pin = “L”, the shutdown switch is activated after the AK4452 is powered up. The internal
circuits will be powered up in 1msec (max) after the activation of the shutdown switch.
(3) The analog output corresponding to digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).
(7) Mute the analog output externally if click noise (3) adversely affect system performance
The timing example is shown in this figure.
(8) The DZF pin is “L” in the internal power-down mode.
Figure 61. Power down/up Sequence Example
Rev. 0.1
- 63 -
2014/04