AK4452VN Datasheet, PDF (69/91 Pages) Asahi Kasei Microsystems – 115dB 768kHz 32-bit 2ch Premium DAC

[AK4452]
(2) Clock Synchronization Sequence with RSTN-bit
The DZF pin outputs “H” by setting RSTN bit to “0”. The DAC is reset after 3~4/fs from the DZF pin = “H”,
and the analog output goes to VREF/2 voltage. The synchronization function is enabled when the DZF pin =
“H”. Figure 66 shows synchronization sequence with RSTN bit.
RSTN bit
Internal
RSTN bit
Internal
State
D/A In
(Digital)
D/A Out
(Analog)
Normal Operation
(3)
GD
DZF
Internal Counter
Reset
Internal
Data Reset
3~4/fs (4)
2~3/fs (4)
Digital Block Power-down
Normal Operation
force”0” (2)
(5)
(5)
GD (3)
Operation (1)
2/fs(4)
4~5/fs (2)
Note:
(1) The DZF pin outputs “H” by a rising edge of RSTN bit, and returns to “L” after 2/fs from the internal
rising edge of RSTN bit. During this period the synchronization function is enabled.
(2) Internal data is fixed to “0” for 4~5/fs forcibly when the internal counter is reset.
(3) The analog output corresponding to digital input has group delay (GD). It is recommended that when
writing “0” data to RSTN bit, “0” period should be longer than the GD period.
(4) It takes 3~4/fs to fall down and 2~3/fs to rise up for the internal RSTN signal from RSTN bit writing.
There is a case that the internal counter is reset before internal RSTN bit is changed to “1” since the
synchronization function becomes enabled immediately by setting RSTN bit = “0”.
(5) A click noise occurs by an internal RSTN signal edge or an internal counter reset. This noise is output
even if “0” data is input. Mute the analog output externally if the click noise adversely affects the system
performance.
Figure 66. Clock Synchronization Sequence with RSTN-bit
Rev. 0.1
- - 69 - -
2014/04