AK4673 Datasheet, PDF (84/107 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP and Touch Screen Controller

[AK4673]
Addr
03H
Register Name
Signal Select 2
Default
D7
D6
D5
D4
D3
D2
D1
D0
LOVL LOPS MGAIN1
0
0
MINL
0
0
0
0
0
0
0
0
0
0
MINL: Switch Control from MIN pin to Stereo Line Output
0: OFF (default)
1: ON
When PMLO bit is “1”, MINL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to VSS1.
MGAIN1: MIC-Amp Gain Control (Table 23)
LOPS: Stereo Line Output Power-Save Mode
0: Normal Operation (default)
1: Power-Save Mode
LOVL: Stereo Line Output Gain Select (Table 51, Table 52)
0: 0dB/+6dB (default)
1: +2dB/+8dB
Addr
04H
Register Name
Mode Control 1
Default
D7
D6
D5
D4
D3
D2
PLL3 PLL2 PLL1 PLL0 BCKO
0
0
0
0
0
0
0
DIF1-0: Audio Interface Format (Table 17)
Default: “10” (Left justified)
BCKO: BICK Output Frequency Select at Master Mode (Table 11)
PLL3-0: PLL Reference Clock Select (Table 5)
Default: “0000”(LRCK pin)
D1
DIF1
1
D0
DIF0
0
Addr
05H
Register Name
Mode Control 2
Default
D7
D6
D5
D4
D3
D2
D1
D0
PS1
PS0
FS3 MSBS BCKP FS2
FS1
FS0
0
0
0
0
0
0
0
0
FS3-0: Sampling Frequency Select (Table 6 and Table 7.) and MCKI Frequency Select (Table 12.)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
BCKP: BICK Polarity at DSP Mode (Table 18)
“0”: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (default)
“1”: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”).
MSBS: LRCK Polarity at DSP Mode (Table 18)
“0”: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (default)
“1”: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change.
PS1-0: MCKO Output Frequency Select (Table 10)
Default: “00”(256fs)
MS0670-E-00
- 84 -
2007/09