AK4673 Datasheet, PDF (17/107 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP and Touch Screen Controller

[AK4673]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
MCKO Output Timing
Frequency
fMCK
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
256fs at fs=32kHz, 29.4kHz
dMCK
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
fs
tLRCKH
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
PLL3-0 bits = “0010”
PLL3-0 bits = “0011”
tBCK
tBCK
Pulse Width Low
Pulse Width High
tBCKL
tBCKH
External Slave Mode
MCKI Input Timing
Frequency 256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Input Timing
Frequency 256fs
fs
512fs
fs
1024fs
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BICK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
min
11.2896
0.4/fCLK
0.4/fCLK
0.2352
40
-
7.35
tBCK−60
45
1/(64fs)
0.4 x tBCK
0.4 x tBCK
7.35
tBCK−60
45
1/(64fs)
130
130
7.35
tBCK−60
45
-
-
0.4 x tBCK
0.4 x tBCK
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
7.35
7.35
7.35
tBCK−60
45
312.5
130
130
typ
max
Units
-
27
MHz
-
-
ns
-
-
ns
-
12.288
MHz
50
60
%
33
-
%
-
48
kHz
-
1/fs − tBCK ns
-
55
%
-
1/(32fs)
ns
-
-
ns
-
-
ns
-
48
kHz
-
1/fs − tBCK ns
-
55
%
-
1/(32fs)
ns
-
-
ns
-
-
ns
-
-
-
1/(32fs)
1/(64fs)
-
-
48
kHz
1/fs − tBCK ns
55
%
-
ns
-
ns
-
ns
-
ns
-
12.288
MHz
-
13.312
MHz
-
13.312
MHz
-
-
ns
-
-
ns
-
48
kHz
-
26
kHz
-
13
kHz
-
1/fs − tBCK Ns
-
55
%
-
-
ns
-
-
ns
-
-
ns
MS0670-E-00
- 17 -
2007/09