AK4673 Datasheet, PDF (74/107 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP and Touch Screen Controller

[AK4673]
[WRITE Operations]
The second byte that followed by address byte consists of the control command byte of the AK4673. The operational
mode is determined by control command. The bit format is MSB first and 8 bits width. Control command is described in
the Table 60. The AK4673 generates an acknowledge after each byte is received. A control command transfer is
terminated by a STOP condition or Repeated Start condition generated by the master. Refer to the Table 60 in detail.
D7
D6
D5
D4
D3
D2
D1
D0
S
A2
A1
A0
X1
PD0
MODE
X2
Figure 70 Control Command Byte (X1, X2 : Don’t care)
SDA _{S Address}
Command
P
Figure 71 Single Write Transmission Sequence
[READ Operation]
The operation mode is determined by the write command just before read operation.
AK4673 features two methods of read operation, single read operation and continuous read operation. The continuous
read operation is a series of single read operation. Each single read operation in continuous read operation makes the
AK4673 updated A/D conversion on each read operation. Write operation does not need to issue before each read
operations are executed.
The channel selection of the AK4673 is defined by the control command just before READ operation. When the
address byte with R/W = “1” read operations are executed. A/D readout format is MSB first, 1byte or 2bytes width.
Upper 8bits are valid on 8-bit mode and upper 12 bits are valid, and lower 4 bits are filled with zero on 12-bit mode.
[Single READ mode]
Read operation begins with a START condition followed by the address byte with R/W= “1”. When the address matches
address byte of the AK4673 (Figure 68), the AK4673 generates ACK. After transmission of the address byte, the master
receives upper 8bit A/D data first, and generates ACK. The AK4673 transmits the remaining 4-bit A/D data and followed
by 4-bit zero data (12bit mode). Master device receives 8bit A/D data (8bit mode). The master then generates NACK and
stop condition or repeated start condition.
SDA S Address
A/D data
A/D data P
Figure 72 Single A/D data Read Sequence (12-bit mode)
MS0670-E-00
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2007/09