AK4673 Datasheet, PDF (79/107 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP and Touch Screen Controller

[AK4673]
B) Audio Control
(1)-1. WRITE Operations
Figure 77 shows the data transfer sequence for the I²C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 66). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant six bits of the slave address are fixed as “001001”. The next bit is CADA (device address
bit). This bit identifies the specific device on the bus. The hard-wired input pin (CADA pin) sets these device address bits
(Figure 78). If the slave address matches that of the AK4673, the AK4673 generates an acknowledge and the operation is
executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the
acknowledge clock pulse (Figure 68). A R/W bit value of “1” indicates that the read operation is to be executed. A “0”
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4673. The format is MSB first, and those most
significant 2-bits are fixed to zeros (Figure 79). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 80). The AK4673 generates an acknowledge after each byte is received. A data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition (Figure 66).
The AK4673 can perform more than one byte write operation per sequence. After receiving of the third byte the AK4673
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 24H prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only be changed when the clock signal on the SCL line is LOW (Figure 67) except for the START and STOP
conditions.
SDA
Slav e
S _Address
Sub
Addr es s ( n)
Data(n)
Data(n+1)
D ata( n+x )
P
Figure 77. Data Transfer Sequence at the I²C-Bus Mode
0
0
1
0
0
1 CADA R/W
( CADA should match with CADA pins)
Figure 78. The First Byte
0
0
A5
A4
A3
A2
A1
A0
Figure 79. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 80. Byte Structure after the second byte
MS0670-E-00
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2007/09