AK4673 Datasheet, PDF (46/107 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP and Touch Screen Controller

[AK4673]
■ ALC Operation
The ALC (Automatic Level Control) is executed by ALC block when ALC bit is “1”. When only DAC is powered-up,
ALC circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, ALC
circuit operates at recording path.
PMADL bit, PMADR bit
“00”
“01”, “10” or “11”
PMDAC bit LOOP bit
Status
0
x
Power-down
1
x
Playback
0
x
Recording
1
0
Recording & Playback
1
Recording Monitor Playback
Table 27. ALC Setting (x: Don’t care)
ALC
Power-down
Playback path
Recording path
Recording path
Recording path
(default)
1. ALC Limiter Operation
During the ALC limiter operation, if either Lch or Rch exceeds the ALC limiter detection level (Table 28), the IVL and
IVR values (same value) are attenuated automatically to the amount defined by the ALC limiter ATT step (Table 29). The
IVL and IVR are then set to the same value for both channels.
When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation
at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing
timeout period of both ALC limiter and recovery operation (Table 30).
When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by
ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
The attenuate operation is executed continuously until the input signal level becomes ALC limiter detection level (Table
28) or less. After completing the attenuation operation, unless ALC bit is changed to “0”, the operation repeats when the
input signal level exceeds LMTH1-0 bits.
LMTH1
0
0
1
1
LMTH0 ALC Limier Detection Level ALC Recovery Waiting Counter Reset Level
0
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
1
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
0
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
1
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 28. ALC Limiter Detection Level / Recovery Counter Reset Level
(default)
ZELMN
0
1
LMAT1 LMAT0
ALC Limiter ATT Step
0
0
1 step
0.375dB
0
1
2 step
0.750dB
1
0
4 step
1.500dB
1
1
8 step
3.000dB
x
x
1step
0.375dB
Table 29. ALC Limiter ATT Step (x: Don’t care)
(default)
ZTM1
0
0
1
1
ZTM0
0
1
0
1
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 30. ALC Zero Crossing Timeout Period
(default)
MS0670-E-00
- 46 -
2007/09