AK4673 Datasheet, PDF (72/107 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP and Touch Screen Controller

[AK4673]
■ Digital I/F
The AK4673 operates with uP via I²C bus and supports the standard-mode (100 KHz) and the fast-mode (400KHz).
Please note that the AK4673 operates in those two modes and does not support a High speed mode I²C-bus system
(3.4MHz). The AK4673 can operate as a slave device on the I²C bus network.
TSVDD=2.6V – 3.6V
Micro-
Rp
Rp
Processor
I²C bus
controller
SCL
SDA
PENIRQN
TSVDD
AK4673
CADT
“L” or “H”
■ Serial Control Interface
Figure 65 Digital I/F
The AK4673 supports the fast-mode I²C-bus (max: 400 kHz). Pull-up resistors at the SDA and the SCL pins should be
connected to (TVDD1/ TSVDD +0.3) V or less voltage. The TVDD1 pin and the TSVDD pin should be connected
together on the same I2C bus.
[Start condition and Stop condition]
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition. All sequences start by the
START condition or Repeated Start Condition. Repeated Start condition is the same signal tradition as Start condition.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All sequences are terminated
by the STOP or Repeated Start condition. Repeated Start is also the Start condition of next transfer so that I²C bus cannot
be idle.
SDA
SCL
S/Sr
S : Start condition
Sr : Repeated start condition
P : stop condition
Figure 66 START and STOP Conditions
[Data transfer]
All commands are preceded by a START condition. After the START condition, a slave address is sent. After the
AK4673 recognizes the START condition, the device interfaced to the bus waits for the slave address to be transmitted
over the SDA line. If the transmitted slave address matches an address for one of the devices, the designated slave device
pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated
by the master device.
[Data validity]
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW except for the START and the STOP condition.
MS0670-E-00
- 72 -
2007/09