English
Language : 

AK4673 Datasheet, PDF (18/107 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP and Touch Screen Controller
◁
[AK4673]
Parameter
Symbol
External Master Mode
MCKI Input Timing
Frequency 256fs
fCLK
512fs
fCLK
1024fs
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
LRCK Output Timing
Frequency
fs
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
tLRCKH
Duty
BICK Output Timing
Period
BCKO bit = “0”
tBCK
BCKO bit = “1”
tBCK
Duty Cycle
dBCK
Audio Interface Timing (DSP Mode)
Master Mode
LRCK “↑” to BICK “↑” (Note 30)
tDBF
LRCK “↑” to BICK “↓” (Note 31)
tDBF
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
tBSD
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
LRCK “↑” to BICK “↑” (Note 30)
tLRB
LRCK “↑” to BICK “↓” (Note 31)
tLRB
BICK “↑” to LRCK “↑” (Note 30)
tBLR
BICK “↓” to LRCK “↑” (Note 31)
tBLR
BICK “↑” to SDTO (BCKP bit = “0”)
tBSD
BICK “↓” to SDTO (BCKP bit = “1”)
tBSD
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Audio Interface Timing (Right/Left justified & I2S)
Master Mode
BICK “↓” to LRCK Edge (Note 30)
tMBLR
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tLRD
BICK “↓” to SDTO
tBSD
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Slave Mode
LRCK Edge to BICK “↑” (Note 31)
tLRB
BICK “↑” to LRCK Edge (Note 32)
tBLR
LRCK Edge to SDTO (MSB)
(Except I2S mode)
tLRD
BICK “↓” to SDTO
tBSD
SDTI Hold Time
tSDH
SDTI Setup Time
tSDS
Min
1.8816
3.7632
7.5264
0.4/fCLK
0.4/fCLK
7.35
-
-
-
-
-
0.5 x tBCK − 40
0.5 x tBCK − 40
−70
−70
50
50
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
0.4 x tBCK
-
-
50
50
−40
−70
−70
50
50
50
50
-
-
50
50
typ
-
-
-
-
-
-
tBCK
50
1/(32fs)
1/(64fs)
50
0.5 x tBCK
0.5 x tBCK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
12.288
13.312
13.312
-
-
48
-
-
-
-
-
0.5 x tBCK + 40
0.5 x tBCK + 40
70
70
-
-
-
-
-
-
80
80
-
-
40
70
70
-
-
-
-
80
80
-
-
Units
MHz
MHz
MHz
Ns
Ns
kHz
ns
%
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 30. MSBS, BCKP bits = “00” or “11”.
Note 31. MSBS, BCKP bits = “01” or “10”.
Note 32. BICK rising edge must not occur at the same time as LRCK edge.
MS0670-E-00
- 18 -
2007/09
 ▷