AK4673 Datasheet, PDF (59/107 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP and Touch Screen Controller

[AK4673]
■ Stereo Line Output (LOUT/ROUT pins)
When DACL bit is “1”, single-ended Lch/Rch signal of DAC is output from the LOUT/ROUT pins. When DACL bit is
“0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10kΩ (min.). When the
PMLO=LOPS bits = “0”, the stereo line output enters power-down mode and the output is pulled-down to VSS1 by
100kΩ(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at power-up/down can be
reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be pulled-down to VSS1 by
20kΩ after AC coupled as Figure 45. Rise/Fall time is 300ms(max) at C=1μF and AVDD=3.3V. When PMLO bit = “1”
and LOPS bit = “0”, stereo line output is in normal operation.
LOVL bit set the gain of stereo line output.
When LOM bit = “1”, DAC output signal is output to LOUT and ROUT pins as (L+R)/2 mono signal.
When LOM3 bit = “1”, the signal selected by MICL3 and MICR3 bits (LIN3/RIN3 inputs or MIC-Amp outputs) to
LOUT and ROUT pins as (L+R)/2 mono signal.
DAC
“DACL”
“LOVL”
LOUT pin
ROUT pin
LOPS
0
1
Figure 44. Stereo Line Output
PMLO
Mode
LOUT/ROUT pin
0
Power-down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 50. Stereo Line Output Mode Select (x: Don’t care)
(default)
LOVL
Gain
Output Voltage (typ)
0
0dB
0.6 x AVDD
(default)
1
+2dB
0.757 x AVDD
Table 51. Stereo Line Output Volume Setting
LOUT 1μF
ROUT
220Ω
20kΩ
Figure 45. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)
MS0670-E-00
- 59 -
2007/09