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AK4673 Datasheet, PDF (16/107 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP and Touch Screen Controller
[AK4673]
DC CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=2.6 ∼ 3.6V, TVDD1=TSVDD=2.5 ∼ 3.6V, TVDD2=1.6 ∼ 3.6V, HVDD=2.6 ∼ 5.25V)
Parameter
Symbol
min
Typ
max
Units
High-Level Input Voltage 2.5V≤TVDD1≤3.6V VIH1 70%TVDD1
-
-
V
2.2V≤TVDD2≤3.6V VIH2 70%TVDD2
-
-
V
1.6V≤TVDD2<2.2V VIH2 75%TVDD2
-
-
V
2.5V≤TSVDD≤3.6V VIH3 70%TSVDD
-
-
V
Low-Level Input Voltage
2.5V≤TVDD1≤3.6V VIL1
-
-
30%TVDD1 V
2.2V≤TVDD2≤3.6V VIL2
-
-
30%TVDD2 V
1.6V≤TVDD2<2.2V VIL2
-
-
25%TVDD2 V
2.5V≤TSVDD≤3.6V VIL3
-
-
30%TSVDD V
High-Level Output Voltage
Except PENIRQN pin (Iout = −200μA) VOHA TVDD1−0.2
-
Except PENIRQN pin (Iout = −200μA) VOHB TVDD2−0.2
-
PENIRQN pin (Iout = −250μA) VOHT TSVDD−0.4
-
-
V
-
V
-
V
Low-Level Output Voltage
(Except SDA and PENIRQN pin: Iout = 200μA) VOL
-
(PENIRQN pin: Iout = 250mA) VOL
-
-
-
0.2
0.4
V
(SDA pin: Iout = 3mA) VOL
-
-
0.4
V
Input Leakage Current
Iin
-
-
±10
μA
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=2.6 ∼ 3.6V; TVDD1 =TSVDD=2.5 ∼ 3.6V; TVDD2=1.6 ~ 3.6V; HVDD=2.6 ∼ 5.25V;
CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
27
MHz
Pulse Width Low
tCLKL 0.4/fCLK
-
-
ns
Pulse Width High
tCLKH 0.4/fCLK
-
-
ns
MCKO Output Timing
Frequency
fMCK
0.2352
-
12.288 MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
-
33
-
%
LRCK Output Timing
Frequency
DSP Mode: Pulse Width High
fs
7.35
tLRCKH
-
-
tBCK
48
kHz
-
ns
Except DSP Mode: Duty Cycle
Duty
-
50
-
%
BICK Output Timing
Period
BCKO bit = “0”
tBCK
-
1/(32fs)
-
ns
BCKO bit = “1”
tBCK
-
1/(64fs)
-
ns
Duty Cycle
dBCK
-
50
-
%
MS0670-E-00
- 16 -
2007/09