AK4673 Datasheet, PDF (31/107 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/HP-AMP and Touch Screen Controller

[AK4673]
■ PLL Slave Mode (AIN3 bit = “0”, PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pin. The required clock to the
AK4673 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 5).
a) PLL reference clock: MCKI pin
BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not
matter. The MCKO pin outputs the frequency selected by PS1-0 bits (Table 10) and the output is enabled by MCKO bit.
Sampling frequency can be selected by FS3-0 bits (Table 6).
AK4673
11.2896MHz, 12MHz, 12.288MHz, 13MHz,
13.5MHz, 19.2MHz, 24MHz, 26MHz,
27MHz
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 19. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS0670-E-00
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2007/09