AK8851 Datasheet, PDF (64/80 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

ASAHI KASEI
Pedestal Level Control Register (R/W) [Sub Address 0x0C]
Fine adjustment of Pedestal Level
Sub Address 0x0C
bit 7
bit 6
DPCC1
DPCC0
0
0
bit 5
DPCT1
0
bit 4
bit 3
DPCT0
BKLVL3
Default Value
0
0
bit 2
BKLVL2
0
[AK8851]
Default Value : 0x00
bit 1
bit 0
BKLVL1
BKLVL0
0
0
Black Level Adjust Register Definition
BIT Register Name
bit 0
BKLVL0
~
~
Black Level
bit 3
BKLVL3
bit 4
DPCT0
~
~
bit 5
DPCT1
Digital Pedestal Clamp Control
bit 6
DPCC0
~
bit 7
~
DPCC1
Digital Pedestal Clamp Coring
Control bit
R/W Definition
See “13.SYNC Separation/SYNC
R/W Detection/Phase-Error Detection/Black Level Fine
Tuning”
[BKLVL3:BKLVL0]-bit
0111 Add 7 code to black Level
0110 Add 6 code to black Level
0101 Add 5 code to black Level
0100 Add 4 code to black Level
0011 Add 3 code to black Level
0010 Add 2 code to black Level
0001 Add 1 code to black Level
0000 Default
1111 Subtract 1 code from black level
1110 Subtract 2 code from black level
1101 Subtract 3 code from black level
1100 Subtract 4 code from black level
1011 Subtract 5 code from black level
1010 Subtract 6 code from black level
1001 Subtract 7 code from black level
1000 Subtract 8 code from black level
Setting of Time constants of the digital pedestal
clamp.
R/W DPCT1:DPCT0
00 : Fast
01 : Middle
10 : Slow
11 : Disable
Setting the non-sensing bandwidth of digital pedestal
R/W clamp.
DPCC1:DPCC0
00 : 1bit
01 : 2bits
10 : 3bits
11 : No non-sensing bandwidth [Default]
MS0244-E-03
64
Confidential
2005 / 07