AK8851 Datasheet, PDF (62/80 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

ASAHI KASEI
Control 2 Register (R/W) [Sub Address 0x09]
Control register to set various functions as shown in the table below.
Sub Address 0x09
bit 7
bit 6
Reserved STUPATOFF
bit 5
ERRHND1
0
0
0
bit 4
bit 3
ERRHND0 Reserved
Default Value
0
0
bit 2
BLUEBACK
0
[AK8851]
Default Value : 0x00
bit 1
bit 0
DPAL1
DPAL0
0
0
Control 2 Register Definitions
BIT Register Name
bit 0
DPAL0
~
~
Deluxe PAL
bit 1
DPAL1
bit 2 BLUEBACK Blue Back output
bit 3 Reserved Reserved bit
bit 4 ERRHND0
~
~
656 Error Handling bit
bit 5 ERRHND1
R/W Definition
R/W Phase Compensation mode. This procedure is also
valid at NTSC mode.
[DPAL1:DPAL0]-bit
00 : Adaptive ON
01 : ON
10 : OFF
11 : Reserved
R/W Output data at the No-signal Input
0 : Black data out
1 : Blue back data out
R/W Reserved
R/W Sets the data handling procedure when AK8850
cannot output the data follow to ITU-R. Bt.656. Error
handling is normally handled on the last lines of the
Frame.
00 : Line Drop/Repeat
01 : Number of Samples of the Last line of the field
is change.
10 : Number of Samples of the Last line of the frame
is change.11 : Reserved
11 : Reserved
bit 6 STUPATOFF Setup Auto Control Off
bit 7 Reserved Reserved bit
Setup Process at the auto signal detection
See. Autodetection
R/W _{0 : Automatic Setup procedure is done}
1 : Automatic Setup procedure is not done
R/W Reserved
MS0244-E-03
62
Confidential
2005 / 07