AK8851 Datasheet, PDF (53/80 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

ASAHI KASEI
AFE Control Register (R/W) [Sub Address 0x00]
[AK8851]
This sets the Analog Front End functions.
Input signal selection and analog clamp control related-tasks are set.
Generation Clamp pulse timing and its pulse width can be adjusted to control the clamp timing of SYNC-Tip clamping.
Sub Address 0x00
Default Value : 0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CLPWIDTH1 CLPWIDTH0 CLPSTAT1 CLPSTAT0 EXTCLP
INSEL2
INSEL1
INSEL0
Default Value
0
0
0
0
0
0
0
0
AFE Control Register Definition
BIT Register Name
bit 0
INSEL0
~
~
Input Select
bit 2
INSEL2
R/W Definition
Set the video input port
[ VBIL2:VBIL0 ] =
R/W 000 : AIN1 (CVBS)
001 : AIN2 (CVBS)
010 : AIN3 (CVBS)
011 : AIN4 (CVBS)
101 : AIN2 Y (YC)
AIN5 C
110: AIN3 Y (YC)
AIN6
111: No Input
When these bits are set 000/001/010/011, ADC2
enters power save mode.
bit 3
EXTCLP
External
Clamp
Configuration
bit 4 CLPSTAT0
~
~
Clamp Slice Level bit
bit 5 CLPSTAT1
bit 6 CLPWIDTH0
~
~
Clamp Pulse Width
bit 7 CLPWIDTH1
When these bits are set 111/100 Clamp/PGA/ADC
enters power save mode.
R/W Attribution of EXTCLP pin
Pin
0: Output the internal clamp timing pulse.
1: Input external clamp timing pulse.
R/W Set the start of clamp timing pulse.
See. [10.CLAMP]
[CLPSTAT1:CLPSTAT0]-bit
00 : Center of Sync signal
01: 1/128H(496nsec) Delay from center of Sync
signal.
10: 1/128H(496nsec) before from center of Sync
signal
11 : 2/128H (1usec) before from center of Sync signal
Set the width of Clamp timing pulse
R/W CLPWIDTH1: CLPWIDTH0
00 : 275nsec
01 : 555nsec
10 : 1.1usec
11 : 2.2usec
MS0244-E-03
53
Confidential
2005 / 07