AK8851 Datasheet, PDF (58/80 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

ASAHI KASEI
Start and Delay Control Register (R/W) [Sub Address 0x05]
Register to set the output data
Sub Address 0x05
bit 7
bit 6
Reserved ACTSTAT2
0
0
bit 5
ACTSTAT1
0
bit 4
bit 3
ACTSTAT0 HALFCKP
Default Value
0
0
[AK8851]
bit 2
YCDELAY2
Default Value : 0x00
bit 1
bit 0
YCDELAY1 YCDELAY0
0
0
0
Start and Delay Control Register Definition
BIT Register Name
bit 0 YCDELAY0
~
~
Y/C Delay Control
bit 2 YCDELAY2
bit 3 HALFCKP HALFCKO Polarity bit
bit 4 ACTSTA0
~
~
Active Video Start Control bit
bit 6 ACTSTA2
bit 7 Reserved Reserved
R/W Definition
R/W Y/C delay setting for output data.
One delay time is 74nsec(1clock@13.5MHz)
Set the value with 2’s complement
[YCDELAY2-YCDELAY0]=
101 : Y-data is 3clocks delay against C-data
110 : Y-data is 2clocks delay against C-data
111 : Y-data is 1clock delay against C-data
000 : No delay [Default]
001 : C-data is 1clock delay against Y-data
010 : C-data is 2clocks delay against Y-data
011 : C-data is 3clocks delay against Y-data
R/W Set the polarity of HALFCKO.
0:
1 : Invert
R/W Set fine adjustment of Start position of decoded video
data.
Set the value with 2’s complement
[ACTSTA2:ACTSTA0]=
101 : Decoding the video data 3pixels earlier.
110 : Decoding the video data 2pixels earlier.
111 : Decoding the video data 1pixel earlier.
000 : Normal position [Default]
001 : Decoding the video data 1pixel delayed.
010 : Decoding the video data 2pixels delayed.
011 : Decoding the video data 3pixels delayed.
R/W Reserved
MS0244-E-03
58
Confidential
2005 / 07