AK8851 Datasheet, PDF (32/80 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

ASAHI KASEI
[AK8851]
21. Vertical Blanking Interval
Setting of Vertical Blanking Interval and selecting tasks to be performed during this interval are set by [Output Format
Register](R/W)[Sub Address 0x02].
Default values of Vertical Blanking Interval are as follows:
525 Line system : Line 1 ~ Line19 and Line 263.5 ~ Line 282.5
625 Line system : Line 623.5 ~ Line 625-Line 1 ~ Line 22 and Line 311 ~ Line 335.5
Vertical Blanking Interval is set by [VBIL2:VBIL0]-bit.
Transition point of V-bit in Video Timing Reference code can be changed by [TRSVSEL]-bit of [Output Format Register].
By properly setting [TRSVSEL]-bit, the transition point of V-bit can be ITU-R BT.656-3, ITU-R BT.656-4 or SMPTE125M
compatible.
During the Vertical Blanking Interval, the default value of the output is set to Black level (Y=0x10,Cb/Cr= 0x80).
By setting [VBIDEC]-bit of [Output Format Register] to “1”, the YC separation function is turned off on those Lines that to
be processed during the Vertical Blanking Interval, and input signal is directly output as a Y signal as in the case of Black
and White mode.
During the Vertical Blanking Interval, the set-up processing is not performed even when [SETUP]-bit of [Input Video
Standard Register] is set.
Bit allocation of [Output Format Register] is shown below.
Sub Address 0x02
bit 7
bit 6
VBIDEC1
VBIDEC0
0
0
bit 5
SLLVEL
0
bit 4
bit 3
TRSVSEL 601LIMIT
Default Value
0
0
bit 2
VBIL2
0
Default Value : 0x00
bit 1
bit 0
VBIL1
VBIL0
0
0
[VBIL2:VBIL0]-bit:
Length of the default Vertical Blanking Interval is adjusted via the[VBIL2:VBIL0]-bit.
* Set Value vs. Vertical Blanking Interval relationship is shown in the following table.
[VBIL2:VBIL0]-bit
Vertical Blanking Interval
525-line system
625-Line system
000
Line 1 ~ Line 19
Line 263.5 ~ Line 282.5
Line 623.5 ~ Line 625 - Line 1 ~ Line 22
Line 311 ~ Line 335.5
001
Line1 ~ Line20
Line263.5 ~ Line 283.5
Line 623.5 ~ Line 625 - Line 1 ~ Line 23
Line 311 ~ Line 336.5
010
Lie 1 ~ Line 21
Line 263.5 ~ Line 284.5
Line 623.5 ~ Line 625 - Line 1 ~ Line 24
Line 311 ~ Line 337.5
011
Line 1 ~ Line 22
Line 263.5~Line 285.5
Line 623.5 ~ Line 625 - Line 1 ~ Line 25
Line 311 ~ Line 338.5
111
Line 1 ~ Line 18
Line 263.5 ~ Line 281.5
Line 623.5 ~ Line 625 - Line 1 ~ Line 21
Line 311 ~ Line 334.5
110
Line 1 ~ Line 17
Line 263.5 ~ Line 280.5
Line 623.5 ~ Line 625 - Line 1 ~ Line 20
Line 311 ~ Line 333.5
101
Line 1 ~ Line 16
Line 263.5 ~ Line 279.5
Line 623.5 ~ Line 625 – Line 1 ~ Line 19
Line 311 ~ Line 332.5
100
LIne-1 ~ Line15
Line 263.5 ~ Line278.5
Line 623.5 ~ Line 625 – Line 1 ~ Line 18
Line 311 ~ Line 331.5
Note
Default
+ 1 Line
+2 Line
+ 3 Line
- 1 Line
- 2 Line
- 3 Line
- 4 Line
[TRSVSEL]-bit:
TRSVSEL-bit is a control bit specify the handling of the V-bit in Rec.656 EAV/SAV code.
This bit performs as in the following table, and is independent of the Vertical Blanking Interval specified by the
[VBIL2:VBIL0]-bit.
MS0244-E-03
32
Confidential
2005 / 07