AK8851 Datasheet, PDF (37/80 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

ASAHI KASEI
[AK8851]
Read Operation of Closed Caption Data:
When the CCRQ-bit is “1”, the AK8851 is placed into a wait state for the Closed Caption data decoding. Data is decoded
as data is received, and after the decoding is completed, ”1” is sent back to CCDET-bit of [Request VBI INFO Register].
CCDET-bit is at “1” right after a reset (it becomes “0” by writing “1” at CCRQ-bit).
The decoded data is then written into [Closed Caption 1 Register](R)[Sub Address 0x1A] and [Closed Caption 2
Register](R)[Sub Address 0x1B] as shown.
Data in [Closed Caption 1 Register] and [Closed Caption 2 Register] are maintained until they are over-written.
Bit allocation of [Closed Caption 1 Register] and [Closed Caption 2 Register] are shown below.
[Closed Caption 1 Register] (R) [Sub Address 0x1A]
bit 7
bit 6
bit 5
bit 4
CC7
CC6
CC5
CC4
bit 3
CC3
bit 2
CC2
bit 1
CC1
bit 0
CC0
[Closed Caption 2 Register] (R) [Sub Address 0x1B]
bit 7
bit 6
bit 5
bit 4
CC15
CC14
CC13
CC12
bit 3
CC11
bit 2
CC10
bit 1
CC9
bit 0
CC8
Closed Caption Extended Data Read Operations:
When the EXTRQ-bit=”1”, the AK8851 is put into a wait state for the Extended Data decoding. Data is decoded as
data is received, and after the decoding is completed, ”1” is sent back to EXTDET-bit of [Request VBI INFO Register].
EXTDET-bit is “1” right after a reset (it becomes “0” by writing “1” at EXTRQ-bit). The decoded data is written into
[Extended Data 1 Register](R)[Sub Address 0x1E] and [Extended Data 2 Register](R)[Sub Address 0x1F] as shown.
Data in [Extended Data 1 Register] and [Extended Data 2 Register] are maintained until they are over-written.
Bit allocation for [Extended Data 1 Register] and [Extended Data 2 Register] are shown below.
[Extended Data 1 Register] (R) [Sub Address 0x1E]
bit 7
bit 6
bit 5
bit 4
EXT7
EXT6
EXT5
EXT4
bit 3
EXT3
bit 2
EXT2
bit 1
EXT1
bit 0
EXT0
[Extended Data 2 Register] (R) [Sub Address 0x1F]
bit 7
bit 6
bit 5
bit 4
EXT15
EXT14
EXT13
EXT12
bit 3
EXT11
bit 2
EXT10
bit 1
EXT9
bit 0
EXT8
Read Operation of VBID Data :
When the VBIDRQ-bit = “1”, the AK8851 is put into a wait state for the VBID data decoding. Data is decoded as data is
received, and after the decoding is completed ”1” is sent back to VBIDDET-bit of [Request VBI INFO Register](R/W)[Sub
Address 0x15].
VBIDDET-bit is at “1” right after a reset (it becomes “0” by writing “1” at VBIDRQ-bit). The decoded 13-bit data is written
into [VBID 1 Register](R)[Sub Address 0x20] and [VBID 2 Register](R)[Sub Address0x21] as shown.
CRCC code is decoded and only the result is stored in register. Data in [VBID1 Register] and [VBID 2 Register] are
maintained until they are over-written.
Bit Allocation of [VBID 1 Register] and [VBID 2 Register] are shown below.
[VBID 1 Register] (R) [Sub Address 0x20]
bit 7
bit 6
bit 5
Reserved Reserved
VBID1
bit 4
VBID2
[VBID 2 Register] (R) [Sub Address 0x21]
bit 7
bit 6
bit 5
VBID7
VBID8
VBID9
bit 4
VBID10
bit 3
VBID3
bit 3
VBID11
bit 2
VBID4
bit 2
VBID12
bit 1
VBID5
bit 1
VBID13
bit 0
VBID6
bit 0
VBID14
MS0244-E-03
37
Confidential
2005 / 07