AK8851 Datasheet, PDF (23/80 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

ASAHI KASEI
[AK8851]
11. CLOCK
The AK8851 operates under the following ,3 clock modes.
(1) Line-Locked Clock Mode
A clock can be derived from the Horizontal SYNC signal (HSYNC) of an input signal. This input signal can be a high
quality source like a Standard Signal Generator or DVD. A clock generated in this way is called Line-Locked Clock. If no
input signal is present while in Line-locked mode, the AK8851 will automatically switch to Fixed-Clock mode.
(2) Frame-Locked Clock Mode
The input signal’s Vertical SYNC can be used to generate a clock when unstable input signals are present, such as
those from typical consumer-grade VCR.
A clock generated in this way is called Frame-Locked Clock. If no input signal is present while in Frame-locked mode,
the AK8851 will automatically switch to Fixed-Clock mode.
(3) Fixed-Clock Mode
This mode is not controlled by the PLL. This mode is enabled only when no signal is fed into the AK8851 or when this
mode is selected via a register setting.
Clock modes are set by [Control 1 Register](R/W)[Sub Address 0x08].
When the clock auto select mode is enabled, the AK8851 automatically shifts its clock mode from/to the Line-locked mode
to/from the Frame-locked mode until it selects an optimum mode It shifts to fixed-clock mode only when no input signal
condition is detected.
Since the AK8851 uses a clock that is synchronized with an input signal in both the Line-locked and Frame-locked clock
modes, ITU-R.656* compatible output is available with input signals of appropriate quality.
PLLs in the AK8851 do not operate when the Fixed-clock mode is selected. The device uses this mode when no input
signal is detected in auto select mode (register setting) . For ITU-R.BT656-compatible output, the input clock must be
synchronized with the input signal.
A detailed description of the clock mode registers [Control 1 Register] is shown below.
Sub Address 0x08
bit 7
bit 6
CLKMODE1 CLKMODE0
bit 5
INTPOL1
0
0
0
bit 4
bit 3
INTPOL0 16BITOUT
Default Value
0
0
bit 2
UVFILSEL
0
Default Value : 0x00
bit 1
bit 0
YCSEP1
YCSEP0
0
0
[CLKMODE1:CLKMODE0] -bit
[CLKMODE1: CLKMODE0 ]
(bit-7: bit-6)
00
01
10
11
Clock mode
Auto Clock mode
Line lock clock
Frame lock clock
Fixed clock mode
Explanation of Clock mode
Optimized clock is selected based on the input video
signal. (default)
Line Lock clock mode
When no signal is input, clock mode changes to Fixed
clock mode.
Frame Lock clock mode.
When no signal is input, clock mode changes to Fixed
clock mode.
Fixed clock mode
MS0244-E-03
23
Confidential
2005 / 07