AK8851 Datasheet, PDF (11/80 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

ASAHI KASEI
[AK8851]
(5) /PD pin release reset
Before setting /PD pin to Low, at least 100 clock cycles must be applied to the device..
After releasing /PD pin to high, the /RESET pin must be kept low until the analog reference voltage and current are
stabilized.
CLK
/R E S E T
/PD
sRES
hRES
VIL
VIH
Parameter
Symbol
Min.
Typ.
Max.
Units
Remark
Set /PD RESET width
sRES
100
CLK Clock Rising Edge
Release /PD Reset width
hRES
10
msec
Note) a 24.576 MHz clock is required for reset operation.
After application of clock, the /RESET pin should be pulled low. This power-on RESET is recommended whenever power is
applied or removed from the AK8851, as applying voltage to the AK8851 cannot ensure proper device initialization. Only a
reset sequence can ensure this.
until.
Output pins except for CLK27MO pin become low during the reset sequence.
(6) Power-On-Reset
At power-on, /RESET pin must be kept low until the analog reference voltage and current are stabilized.
DVDD
AV D D
3.0V
/RESET
VIL
pRES_PON
Parameter
Symbol
Min.
Typ.
Max.
Units
Remark
/RESET pulse width pRES_PON
10
msec
Note) For reset operation, a 24.576 MHz clock is required.
System control pins ( SELA,CLKINV,/PD ) must be kept valid until the 10-clock time after the rising edge of reset
pulse.
Output pins except for CLK27MO pin become low during the reset sequence.
MS0244-E-03
11
Confidential
2005 / 07