AK8851 Datasheet, PDF (13/80 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

ASAHI KASEI
[AK8851]
6. Functional Summary
(1) Clock
The AK8851 operates in one of 3 clock modes.
1. Line Locked Clock mode:
An operating mode where the device uses a clock that is synchronized with the Horizontal Sync signal for each line.
2.Frame Locked Clock mode:
The device operates by a clock that is synchronized with the Vertical Sync signal for each Frame.
3.Fixed Clock mode:
An operating mode where the device operates by an asynchronous clock.
These clock modes are set by the [Control 1 register].
Since both Line Locked and Frame Locked modes use an input-signal synchronized clock, ITU-R BT.656* compatible
output is available (however ,depending upon the input signal quality, ITU-R BT.656 may not be satisfied ).
(2) Analog Interface
The AK8851 accepts Composite and discrete Y/C signals (S-video) as input. 6 channels are assigned for these input pins.
Channel selection is set via register.
The following input signal combinations are possible.
(a) select a single channel from composite video signal x 4
(b) select a single channel from composite signal x 2 + S-video signal input x2
(3) Input Signals
The device accepts NTSC-M,NTSC-4.43,PAL-B,D,G,H,I,N,NcM,60,SECAM composite video signals and S Video
signals.
It is also possible to accept an input signal with set-up features by setting the set-up register bit. In this case, the set-up is
set at the 7.5% point. The automatic input signal detect function is also enabled via register settings.
Required input signal quality is as follows.
(3-1) input signal quality
Item
Video Input Level
Color Burst Level
Input Range
+/- 6
+/-10
Unit
Conditions
dB Video signal should be input with -6dB level
dB
(divided be the resistor), and through 0.1uF
capacitor.)
(3-2) Non-Standard input signal treatment
Item
Process
Lack of HSYNC
Running with self timing
Lack of VSYNC
Running with self timing
B/W Video Signal input
Set register to B/W mode .
Auto transition to B/W mode in auto signal detection mode.
Macrovision
Information with Macrovision control register.
Certified Macrovision device .
(4) Analog Input Signal Processing
Input Selector ( inter-channel isolation ): better than –60 dB
PGA : 0 ~ 12 dB ( approx. 0.1 dB/step)
AD converter : operates at 27 MHz
For normal operation, the Frame-locked PLL generates by the Line-locked PLL or a required internal clock.
(5) Clamp processing
Analog Sync-Tip clamping is done and the Digital signal-processing block processes the Digital Pedestal clamping.
(6) AGC function
The AGC adjusts the input signal level based on the amplitude difference between the Sync-Tip level and the Pedestal
level of the input signal.
(7) ACC function
The ACC adjusts the input color signal level based on the color burst level of the input signal. ACC does not function for
SECAM signals.
MS0244-E-03
13
Confidential
2005 / 07