AK8851 Datasheet, PDF (21/80 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

ASAHI KASEI
[AK8851]
10.CLAMP
[Analog Clamp circuit]:
The AK8851 uses an analog circuit to clamp the input signal to the Sync-Tip level (Analog Sync-Tip clamp). Clamp timing
is set by [AFE Control Register](R/W)[Sub Address 0x00].
The clamp timing pulse is generated for a fixed time specified by [AFE Control Register] at the falling edge of SYNC
signal as a starting point that is SYNC-separated within the AK8851. The Pedestal clamp of A to D converted input data is
then processed in the digital signal-processing block (Digital Pedestal Clamp). The Digital Pedestal Clamp is described in a
later section.
Analog SYNC-Tip clamping is set by [AFE Control Register](R/W)[Sub Address 0x00].
[AFE Control Register] sets the timing of the SYNC-Tip clamp in the AK8851.
This adjusts the start timing of the clamp and its pulse width.
Sub Address 0x00
bit 7
bit 6
CLPWIDTH1 CLPWIDTH0
0
0
bit 5
CLPSTAT1
0
bit 4
bit 3
CLPSTAT0 EXTCLP
Default Value
0
0
bit 2
INSEL2
0
Default Value : 0x00
bit 1
bit 0
INSEL1
INSEL0
0
0
MS0244-E-03
21
Confidential
2005 / 07