AK8851 Datasheet, PDF (15/80 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

ASAHI KASEI
[AK8851]
7. Input Signal Selector
The AK8851 has 4 analog signal input pins. Signal selection is done by [AFE Control Register](R/W)[Sub Address 0x00]
and the type of Video signals to be decoded is set by [Input Video Standard Register](R/W)[Sub Address 0x01]. Video
signals to be decoded by the AK8851 are NTSC, NTSC-4.43, PAL B, D, G, H, I, M, N, 60 and SECAM.
It is also possible to automatically distinguish input signal types by setting the AUTODET-bit of [Input Video Standard
Register].
However Automatic detections of Black and White signals and those with / without the SETUP features are not possible.
Input signals are converted into Digital codes as follows:
Composite Video signal: After it conversion to digital data through the functional blocks shown in Fig.2 Analog Block
description,
CLAMP1 BLOCK --- PGA1 BLOCK --- ADC1 BLOCK,
It is then processed in the Digital Block.
Discrete Y/C Video signal input (S-Video signal input):
The input Luminance Signal (Y) is converted into digital data through the functional blocks shown in Fig.2 Analog Block
description,
CLAMP1 BLOCK --- PGA1 BLOCK --- ADC1 BLOCK
and the Input Chroma Signal (C) is converted in digital data through
CLAMP2 BLOCK --- PGA2 BLOCK --- ADC2 BLOCK,
then each digital data is processed in the Digital block.
The following describes the Register Setting of [AFE Control Register](R/W)[Sub Address 0x00] and [Input Video Standard
Register](R/W)[Sub Address 0x01].
[AFE Control Register](R/W)[Sub Address 0x00]:
this register sets the input signal.
Its Bit Allocation is shown below:
Sub Address 0x00
bit 7
bit 6
CLPWIDTH1 CLPWIDTH0
0
0
bit 5
CLPSTAT1
0
bit 4
bit 3
CLPSTAT0 EXTCLP
Default Value
0
0
bit 2
INSEL2
0
Default Value : 0x00
bit 1
bit 0
INSEL1
INSEL0
0
0
[INSEL2 : INSEL0]-bit:
to set the input port of input signal.
The setting is done as follows. This input port setting also controls the Analog Block’s Power Saving mode.
[INSEL2:INSEL0]
Select Input port
Input Video
Power Save
[000]
AIN1
CVBS
[001]
[010]
AIN2
AIN3
CVBS
CVBS
ADC2 set to Power save mode.
[011]
AIN4
CVBS
[101]
AIN2/AIN5
AIN2: Y
AIN5: C
[110]
AIN3/AIN6
AIN3: Y
AIN6: C
[100] [111]
No signal in
ADC1 and ADC2 are set to Power save
mode.
Note: when [INSEL2:INSEL0]-bit is set to [1,0,0] or [1,1,1], ADC1 and ADC2 in Power Saving mode, including the CLAMP
and PGA blocks (timing signal outputs are driven by the self-running clock as the digital blocks are in normal
operating mode).
MS0244-E-03
15
Confidential
2005 / 07