AK8851 Datasheet, PDF (22/80 Pages) Asahi Kasei Microsystems – NTSC/PAL/SECAM Digital Video Decoder

ASAHI KASEI
[AK8851]
[CLPSTAT1:CLPSTAT0]-bit:
This sets the clamp position of input signal. The clamp timing pulse position is internally generated by the AK8851. Clamp
timing pulse is generated at the center position of SYNC signal. Its pulse position is adjustable(refer to Fig.5).
[CLPSTAT1:CLPSTAT0]-bit
Start position of Clamp timing pulse [clock counts] Note
[00]
Center of Sync signal
[01]
1/128H(496nsec) Delay from center of Sync signal.
[10]
1/128H(496nsec) before from center of Sync signal
[11]
2/128H (1usec) before from center of Sync signal
[CLPWIDTH1:CLPWIDTH0]-bit:
This sets the clamp timing pulse width for the input signal.
*Pulse Width is set by [CLPWIDTH1:CLPWIDTH0]-bit (refer to Fig.5)
[CLPWIDTH1:CLPWIDTH0]-bit
Width of clamp timing pulse [clock counts]
[00]
275nsec
[01]
555nsec
[10]
1.1usec
[11]
2.2usec
Note
C LPSTA T[1:0] = 00
C LPSTA T[1:0] = 01
C LPSTA T[1:0] = 10
C LPSTA T[1:0] = 11
C LPW ID TH [1:0]
1 /1 2 8 H
1 /1 2 8 H
2 /1 2 8 H
F ig.5 C lam p tim ing pu lse
[EXTCLP]-bit:
This sets the attributes of the EXTCLP pin. Input/Output selection of EXTCLP pin is done by [EXTCLP]-bit register settings.
By switching the pin function, it is possible to output an internally- generated Clamp timing pulse or to clamp the input signal
by an externally generated Clamp timing pulse.
[EXTCLP]-bit
Attribution of EXTCLP
Note
0
Output the clamp timing pulse of internal pulse generator Default
1
Input external clamp timing pulse.
MS0244-E-03
22
Confidential
2005 / 07