AK4536 Datasheet, PDF (57/59 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4536]
3. PLL & Slave mode
PMPLL bit
(Addr:01H,D5)
External BICK
External FCK
(1)
(2)
Input
(2)
Input
Example
: ^{Audio I/F Format : DSP Mode, BCKP = MSBS = “0”}
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 8kHz
(1) Addr:01H, Data:04H
(2) Stop the external clocks
Figure 42. Stop of Clock Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and FCK clocks.
4. EXT mode
(1)
MCKPD bit
(Addr:01H,D7)
(1)
PMXTL bit
(Addr:01H,D1)
"H" or "L"
(2)
External MCKI
Input
(2)
External BICK
Input
External FCK
(2)
Input
Example
: ^{Audio I/F Format :MSB justified(ADC and DAC)}
Input MCKI frequency:1024fs
MCKI pin: CMOS Level
Sampling Frequency:8kHz
(1) Addr:01H, Data:04H
(2) Stop the external clocks
Figure 43. Stop of Clock Sequence (4)
<Example>
(1) Pull down the MCKI pin: MCKPD bit = “0” → “1”
Power down X’tal: PMXTL bit = “1” → “0”
When the external master clock becomes Hi-Z or the external master clock is input by AC couple, MCKI pin
should be pulled down. When the external master clock is input by AC couple, X’tal should be
powered-down.
(2) Stop the external MCKI, BICK and FCK clocks
n Power down
Power down VCOM (PMVCM= “1” → “0”) after all blocks except VCOM are powered down and a master clock stops.
The AK4536 is also powered-down by PDN pin = “L”. When PDN pin = “L”, the registers are initialized.
MS0174-E-00
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2002/09