AK4536 Datasheet, PDF (48/59 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4536]
SYSTEM DESIGN
Figure 33 shows the system connection diagram. An evaluation board [AKD4536] is available which demonstrates the
optimum layout, power supply arrangements and measurement results.
C
1µ
1µ
C
1µ
2.2k
R
Analog Supply
2.4∼3.6V
2.2µ+
10µ ₊
0.1µ
0.1µ
4.7n 10k
1 VCOM
2 AVSS
3 AVDD
4 VCOC
5 PDN
6 CSN
7 CCLK
Top View
MIN 21
SVSS 20
SVDD 19
SPN 18
+
0.1µ 10µ
SPP 17
C
XTO 16
MCKI/XTI 15
C
Analog Supply
2.4∼3.6V
8Ω (Speaker)
10
0.1µ
+ _10µ
DSP or µP
Figure 33. Typical Connection Diagram
Notes:
- AVSS, DVSS and SVSS of the AK4536 should be distributed separately from the ground of external controllers.
- All digital input pins except pull-down pin should not be left floating.
- Value of R and C in Figure 33 should depend on system.
- When the AK4536 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.
- When the AK4536 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 34.
Mode
0
1
2
3
4
5
6
7
PLL2 PLL1 PLL0 PLL Reference
bit
bit bit Clock Input Pin
Input
Frequency
Rp and Cp of
VCOC pin
Rp[Ω] Cp[F]
0
0
0
FCK pin
1fs
10k 470n
0
0
1
BICK pin
16fs
10k 4.7n
0
1
0
BICK pin
32fs
10k 4.7n
0
1
1
BICK pin
64fs
10k 4.7n
1
0
0 MCKI/XTI pin 11.2896MHz 10k 4.7n
1
0
1 MCKI/XTI pin 12.288MHz 10k 4.7n
1
1
0 MCKI/XTI pin
12MHz
10k 4.7n
1
1
1
N/A
N/A
-
-
Table 34. Setting of PLL Mode (*fs: Sampling Frequency)
MS0174-E-00
- 48 -
2002/09