AK4536 Datasheet, PDF (33/59 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4536]
n Speaker Output
The output signal from DAC is input to the Speaker-amp via the ALC2 circuit. This Speaker-amp is a mono output
controlled by BTL and a gain of the Speaker-Amp is set by SPKG bit. When SPKG bit is “0”, output power is a maximum
of 150mW@8Ω and SVDD = 3.3V. When SPKG bit is “1”, output power is a maximum of 250mW@8Ω and SVDD =
3.3V.
Speaker blocks (MOUT, ALC2 and Speaker-amp) can be powered-up/down by controlling the PMSPK bit. When the
PMSPK bit is “0”, the MOUT, SPP and SPN pins are placed in a Hi-Z state.
When the PMSPK bit is “1” and SPPS bit is “0”, the Speaker-amp enters power-save-mode. In this mode, the SPP pin is
placed in a Hi-Z state and the SPN pin goes to SVDD/2 voltage. And then the Speaker output gradually changes to the
SVDD/2 voltage and this mode can reduce pop noise at power-up. When the AK4536 is powered-down, pop noise can be
also reduced by first entering power-save-mode.
PMSPK bit
SPPS bit
SPP pin
Hi-Z
Hi-Z
SPN pin Hi-Z ^SVDD/2
Figure 29. Power-up/Power-down Timing for Speaker-Amp
SVDD/2
Hi-Z
n MONO LINE OUTPUT (AOUT pin)
A signal of DAC is output from AOUT pin. When the DACA bi is “0”, this output is OFF and the AOUT pin is forced to
VCOM voltage. The load resistance is 10kΩ(min). When PMAO bit is “0”, the mono line output enters power-down and
the output is placed in a Hi-Z state.
MS0174-E-00
- 33 -
2002/09