AK4536 Datasheet, PDF (10/59 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4536]
Parameter
Symbol
min
typ
max
PLL Slave Mode (PLL Reference Clock = BICK pin) (See Figure 6, Figure 7, Figure 8 and Figure 9)
FCK Frequency
fFCK
7.35
26
Pulse width High
tFCKH tBCK-60
1/fFCK-tBFCK
BICK Period (PLL2-0 = “001”)
tBCK
1/16fFCK
(PLL2-0 = “010”)
tBCK
1/32fFCK
(PLL2-0 = “011”)
tBCK
1/64fFCK
BICK Pulse Width Low
tBCKL 0.4 x tBCK
Pulse Width High
tBCKH 0.4 x tBCK
FCK “↑” to BICK “↑” (Note 21)
tFCKB 0.4 x tBCK
FCK “↑” to BICK “↓” (Note 22)
tFCKB 0.4 x tBCK
BICK “↑” to FCK “↑” (Note 21)
tBFCK 0.4 x tBCK
BICK “↓” to FCK “↑” (Note 22)
tBFCK 0.4 x tBCK
BICK “↑” to SDTO (BCKP = “0”)
tBSD
80
BICK “↓” to SDTO (BCKP = “1”)
tBSD
80
SDTI Hold Time
tSDH
60
SDTI Setup Time
tSDS
60
EXT Slave Mode (See Figure 10 and Figure 11)
MCKI Frequency: 256fs
fCLK
1.8816
2.048
6.656
512fs
fCLK
3.7632
4.096
13.312
1024fs
fCLK
7.5264
8.192
13.312
Pulse Width Low
tCLKL 0.4/fCLK
Pulse Width High
tCLKH 0.4/fCLK
AC Pulse Width (Note 23)
tACW 0.4/fCLK
FCK Frequency (MCKI = 256fs or 512fs)
fFCK
7.35
8
26
(MCKI = 1024fs)
fFCK
7.35
8
13
Duty
duty
45
55
BICK Period
tBCK
600
BICK Pulse Width Low
tBCKL
240
Pulse Width High
tBCKH
240
FCK Edge to BICK “↑” ”
(Note 24)
tFCKB
50
BICK “↑” to FCK Edge
(Note 24)
tBFCK
50
FCK to SDTO (MSB) (Except I²S mode)
tFSD
80
BICK “↓” to SDTO
tBSD
80
SDTI Hold Time
tSDH
50
SDTI Setup Time
tSDS
50
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 21. MSBS, BCKP bits = “00” or “11”
Note 22. MSBS, BCKP bits = “01” or “10”
Note 23. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground.
(Refer to Figure 3)
Note 24. BICK rising edge must not occur at the same time as FCK edge.
MS0174-E-00
- 10 -
2002/09