AK4536 Datasheet, PDF (20/59 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4536]
n PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL2-0
and FS2-0 bits. The PLL lock time is shown in Table 3, whenever the AK4536 is supplied to a stable clocks after PLL is
powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes.
1) Select PLL/ EXT Mode
PMPLL bit
Mode
0
EXT Mode
1
PLL Mode
Table 2. Select PLL/EXT Mode
Default
2) Setting of PLL Mode
Mode
PLL2
bit
PLL1
bit
0
0
0
1
0
0
2
0
1
3
0
1
4
1
0
5
1
0
6
1
1
7
1
1
PLL0 PLL Reference
bit Clock Input Pin
Input
Frequency
R and C of VCOC
pin
R[Ω] C[F]
0
FCK pin
1fs
10k 470n
1
BICK pin
16fs
10k 4.7n
0
BICK pin
32fs
10k 4.7n
1
BICK pin
64fs
10k 4.7n
0 MCKI/XTI pin 11.2896MHz 10k 4.7n
1 MCKI/XTI pin 12.288MHz 10k 4.7n
0 MCKI/XTI pin
12MHz
10k 4.7n
1
N/A
N/A
-
-
Table 3. Setting of PLL Mode (*fs: Sampling Frequency)
PLL Lock
Time
(max)
160ms
2ms
2ms
2ms
40ms
40ms
40ms
-
Default
3) Setting of sampling frequency in PLL Mode.
When PLL2 bit is “1” (PLL reference clock input is XTI/MCKI pin), the sampling frequency is selected by FS2-0 bits as
defined in Table 4.
Mode
FS2 bit
FS1 bit
FS0 bit Sampling Frequency
0
0
0
0
8kHz
Default
1
0
0
1
12kHz
2
0
1
0
16kHz
3
0
1
1
24kHz
4
1
0
0
N/A
5
1
0
1
11.025kHz
6
1
1
0
N/A
7
1
1
1
22.05kHz
Table 4. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL = “1”
When PLL2 bit is “0” (PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS1-0
bits. (See Table 5). FS2 bit is ignored.
Mode FS1 bit FS0 bit Sampling Frequency Range
0
0
0
7.35kHz ≤ fs ≤ 10kHz Default
1
0
1
10kHz < fs ≤ 14kHz
2
1
0
14kHz < fs ≤ 20kHz
3
1
1
20kHz < fs ≤ 26kHz
Table 5. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL = “1”
MS0174-E-00
- 20 -
2002/09