AK4536 Datasheet, PDF (21/59 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4536]
n PLL Unlock
1) PLL, Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, irregular frequency clocks are output from FCK and BICK pins after PMPLL bit = “0” à “1”. After that PLL
is unlocked, BICK and FCK pins output “L” for a moment. (See Table 6) Therefore a first period of FCK and BICK may
be irregular clock, but these clocks return to normal after a period of 1/fs.
BICK pin
FCK pin
Master Mode (M/S bit = “1”)
After that PMPLL “0” à “1”
PLL Unlock
Irregular clock output
“L” Output
Irregular clock output
“L” Output
Table 6. Clock Operation at Master & PLL Mode
PLL Lock
See Table 9
1fs Output
2) PLL, Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, ADC and DAC are output to abnormal data when the PLL is unlocked. For DAC, the output signal should be
muted by writing “0” to DACA and DACM bits in Addr=02H.
n Master Mode/Slave Mode
The M/S bit selects either master or slave modes. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4536 is power-down mode (PDN pin = “L”) and exits reset state, the AK4536 is slave mode. After exiting reset state,
the AK4536 goes master mode by changing M/S bit = “1”.
When the AK4536 is used by master mode, FCK and BICK pins are a floating state until M/S bit becomes “1”. FCK and
BICK pins of the AK4536 should be pulled-down or pulled-up by about 100kΩ resistor externally to avoid the floating
state.
M/S bit
Mode
0
Slave Mode
Default
1
Master Mode
Table 7. Select Master/Salve Mode
MS0174-E-00
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2002/09