AK4536 Datasheet, PDF (23/59 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4536]
2) PLL, Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is input from BICK or FCK pins. The required clock to the AK4536 is generated by an internal
PLL circuit. Input frequency is selected by PLL2-0 bits. Sampling frequency corresponds to 7.35kHz ∼ 26kHz by changing
FS1-0 bits. (See Table 5)
Audio interface format corresponds to Mode 0 (DSP Mode) only.
AK4536
XTO
MCKI/XTI
BICK
FCK
SDTO
SDTI
DSP or µP
16fs, 32fs, 64fs
1fs
BCLK
FCK
SDTI
SDTO
Figure 19. PLL & Slave Mode
The external clocks (BICK and FCK) should always be present whenever the ADC or DAC is in operation (PMADC bit =
“1” or PMDAC bit = “1”). If these clocks are not provided, the AK4536 may draw excess current and it is not possible to
operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and
DAC should be in the power-down mode (PMADC bit =PMDAC bit = “0”).
MS0174-E-00
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2002/09