AK4536 Datasheet, PDF (56/59 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
n Stop of Clock
Master clock can be stopped when ADC, DAC, ALC1 and ALC2 don’t operate.
1. When X’tal is used in PLL & Master mode.
[AK4536]
PMXTL bit
(Addr:01H,D1)
(1)
PMPLL bit
(Addr:01H,D0)
MCKPD bit
(Addr:01H,D2)
Example:
Audio I/F Format: DSP Mode, BCKP = MSBS = “0”
BICK frequency at Master Mode : 64fs
Input Master Clock Select at PLL Mode : 11.2896MHz
Sampling Frequency:8kHz
(1) Addr:01H, Data:0CH
Figure 40. Stop of Clock Sequence (1)
<Example>
(1) Power down X’tal and PLL: PMXTL bit = PMPLL bit = “1” → “0”
Pull down the XTI pin: MCKPD bit = “0” → “1”
2. When an external clock is used in PLL & Master mode
PMPLL bit
(Addr:01H,D5)
PMXTL bit
(Addr:01H,D1)
MCKPD bit
(Addr:01H,D7)
External MCKI
"H" or "L"
Input
(1)
(2)
(2)
(3)
Example:
Audio I/F Format: DSP Mode, BCKP = MSBS = “0”
BICK frequency at Master Mode : 64fs
MCKI pin: CMOS Level
Input Master Clock Select at PLL Mode : 11.2896MHz
Sampling Frequency:8kHz
(1) (2)Addr:01H, Data:0CH
(2) Stop an external MCKI
Figure 41. Stop of Clock Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Pull down the MCKI pin: MCKPD bit = “0” → “1”
Power down X’tal: PMXTL bit = “1” → “0”
When the external master clock becomes Hi-Z or the external master clock is input by AC couple, MCKI pin
should be pulled down. When the external master clock is input by AC couple, X’tal should be
powered-down.
(3) Stop an external master clock
MS0174-E-00
- 56 -
2002/09