AK4536 Datasheet, PDF (52/59 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4536]
3. When the external clocks (FCK and BICK pins) is used in PLL & Slave mode.
Power Supply
PDN pin
PMVCM bit
(Addr:00H,D6)
MCKPD bit
(Addr:01H,D2)
PMXTL bit
(Addr:01H,D1)
PMPLL bit
(Addr:01H,D0)
FCK, BICK
Internal Clock
(1)
(2) (3)
(4) "H"
Example:
Audio I/F Format : DSP Mode, BCKP = MSBS = “0”
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 8kHz
4f₍s₁o₎ f_{Power Supply & PDN pin = “L” à “H”}
(4) "L"
(2) Addr:04H, Data:30H
Addr:05H, Data:00H
Input
(5)
(3) Addr:00H, Data:40H
(4) Addr:01H, Data:05H
(6)
Figure 36. Clock Set Up Sequence (3)
BICK and FCK input
<Example>
(1)After Power Up, PDN pin “L” à “H”
“L” time(1) of 150ns or more is needed to reset the AK4536.
(2)DIF1-0, FS2-0, PLL2-0, MSBS and BCKP bits should be set during this period.
(3)Power Up VCOM: PMVCM bit = “0” à “1”
VCOM should first be powered up before the other block operates.
(4)Pull down the XTI pin: MCKPD bit = “1”
Power Down X’tal: PMXTL bit = “0”
(5)PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (FCK or BICK pin) is supplied.
PLL lock time is 160ms(max) when FCK is a PLL reference clock. And PLL lock time is 2ms(max) when BICK
is a PLL reference clock.
(6)The AK4536 starts to output the FCK and BICK clocks after the PLL becomes stable. The normal operation of the
block which a clock is necessary for becomes possible.
MS0174-E-00
- 52 -
2002/09