AK4536 Datasheet, PDF (31/59 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4536]
[3] Example of ALC1 Operation
Table 15 shows the examples of the ALC1 setting.
Register Name
LMTH
LTM1-0
ZELM
ZTM1-0
WTM1-0
REF6-0
IPGA6-0
LMAT1-0
RATT
ALC1
Comment
fs=8kHz
Data
Operation
Limiter detection Level
1
-4dBFS
Limiter operation period at ZELM = 1
00
Don’t use
Limiter zero crossing detection
0
Enable
Zero crossing timeout period
00
16ms
Recovery waiting period
*WTM1-0 bits should be the same data
00
16ms
as ZTM1-0 bits
Maximum gain at recovery operation
47H
+27.5dB
Gain of IPGA
47H
+27.5dB
Limiter ATT Step
00
1 step
Recovery GAIN Step
0
1 step
ALC1 Enable bit
1
Enable
Table 15. Examples of the ALC1 Setting
fs=16kHz
Data Operation
1
-4dBFS
00
Don’t use
0
Enable
01
16ms
01
16ms
47H
+27.5dB
47H
+27.5dB
00
1 step
0
1 step
1
Enable
The following registers should not be changed during the ALC1 operation. These bits should be changed, after the ALC1
operation is finished by ALC1 bit = “0” or PMMIN bit = “0”.
• LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits
Manual Mode
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms @ fs= 8kHz
Limiter and Recovery Step = 1
Maximum Gain = +27.5dB
Limiter Detection Level = -4dBFS
ALC2 bit = “1” (default)
WR (ZTM1-0, WTM1-0, LTM1-0)
(1) Addr=06H, Data=00H
WR (REF6-0)
(2) Addr=08H, Data=47H
WR (IPGA6-0) ^{* The value of IPGA should be}
the same or smaller than REF’s
WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM)
(3) Addr=09H, Data=47H
(4) Addr=07H, Data=61H
ALC1 Operation
Note : WR : Write
Figure 28. Registers set-up sequence at the ALC1 operation
MS0174-E-00
- 31 -
2002/09