AK4536 Datasheet, PDF (50/59 Pages) Asahi Kasei Microsystems – 16-Bit Mono CODEC with ALC & MIC/SPK-AMP

ASAHI KASEI
[AK4536]
CONTROL SEQUENCE
n Clock Set up
When ADC, DAC, ALC1 and ALC2 are used, the clocks must be supplied.
1. When X'tal is used in PLL & Master mode.
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
MCKPD bit
(Addr:01H, D2)
PMXTL bit
(Addr:01H, D1)
PMPLL bit
(Addr:01H, D0)
BICK, FCK
(1)
(2) (3)
(4)
(5)
20ms(typ)
(7)
40msec(max)
(6)
1msec(max)
Output
Example:
: ^{Audio I/F Format: DSP Mode, BCKP = MSBS = “0”}
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode : 11.2896MHz
Sampling Frequency:8kHz
(1) Power Supply & PDN pin = “L” à “H”
(2)Addr:01H, Data:0CH
Addr:04H, Data:48H
Addr:05H, Data:00H
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:0BH
BICK and FCK output
Figure 34. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin = “L” à “H”
“L” time (1) of 150ns or more is needed to reset the AK4536.
(2) DIF1-0, PLL2-0, FS2-0, BCKO1-0, MSBS, BCKP and M/S bits should be set during this period.
(3) Power UpVCOM: PMVCM bit = “0” à “1”
VCOM should first be powered up before the other block operates.
(4) Release the pulled-down of the XTI pin: MCKPD bit = “1” → “0”
Power Up X’tal: PMXTL bit = “0” → “1”
Power Up the PLL: PMPLL bit = “0” → “1”
(5) It takes X’tal oscillator 20ms(typ) to be stable after PMXTL bit=“1”. This time depends on X’tal. PLL lock time
is 40ms(max) after PMPLL bit changes from “0” to “1”.
(6) The AK4536 starts to output the FCK and BICK clocks after the PLL becomes stable. The normal operation of
the block which a clock is necessary for becomes possible.
(7) The irregular frequencies are output from FCK and BICK pins in this section.
MS0174-E-00
- 50 -
2002/09