AK5365 Datasheet, PDF (38/41 Pages) Asahi Kasei Microsystems – 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl

ASAHI KASEI
[AK5365]
SYSTEM DESIGN
Figure 24 shows the system connection diagram. An evaluation board is available which demonstrates application circuits,
the optimum layout, power supply arrangements and measurement results.
• Master Mode, 3-wire control (CTRL pin = “L”)
1µ
1µ
1µ
1µ
1µ
47k
47k
47k
47k
47k
44 43 42 41 40 39 38 37 36 35 34
1µ _47k
1 LIN5
1µ _47k
2 TEST1
3 LIN4
1µ _47k
4 TEST2
5 LIN3
1µ _47k
6 TEST3
7 LIN2
1µ _47k
8 TEST4
9 LIN1
10 LOPIN
24k
11 LOUT
Top View
CSN/CAD1 33
CCLK/SCL 32
CDTI/SDA 31
SEL2 30
SEL1 29
SEL0 28
SMUTE 27
ALC 26
PDN 25
MCLK 24
LRCK 23
4.7µ
12 13 14 15 16 17 18 19 20 21 22
4.7µ ^24k
0.1µ 0.1µ
0.1µ
10µ 2.2µ
10µ
Reset
DSP and uP
Analog Supply
4.75 ~ 5.25V
Digital Supply
3.0 ~ 5.25V
Note:
- AVSS and DVSS of the AK5365 should be distributed separately from the ground of external digital devices
(MPU, DSP etc.).
- When LOUT/ROUT drives a capacitive load, resistors should be added in series between LOUT/ROUT
and capacitive load.
- All input pins except pull-down pin (ALC, SMUTE pins) should not be left floating.
Figure 24. Typical Connection Diagram
MS0164-E-01
- 38 -
2002/08