AK5365 Datasheet, PDF (21/41 Pages) Asahi Kasei Microsystems – 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl

ASAHI KASEI
[AK5365]
„ Input Volume
The AK5365 includes two independent channel analog volumes (IPGA) with 25 levels at 0.5dB steps located in front of
the ADC. The digital volume controls (DATT) have 128 levels (including MUTE) and is located after the ADC. Both the
analog and digital volumes are controlled through the same register address. When the MSB of the register is “1”, the
IPGA changes and when the MSB = “0”, the DATT changes.
The IPGA is a true analog volume control that improves the S/N ratio as seen in Table 10. Independent zero-crossing
detection is used to ensure level changes only occur during zero-crossings. If there are no zero-crossings, the level will then
change after a time-out period (Table 11); the time-out period scales with fs. If a new value is written to the IPGA register
before the IPGA changes at the zero crossing or time-out, the previous value becomes invalid. The timer (channel
independent) for time-out is reset and the timer restarts for new IPGA value.
The DATT is a pseudo-log volume that is linear-interpolated internally. When changing the level, the transition between
ATT values has 8031 levels and is done by soft changes, eliminating any switching noise.
Input Gain Setting
0dB
+6dB
fs=48kHz, A-weight
103dB
100dB
Table 10. PGA+ADC S/N
+12dB
96dB
ZTM1
0
0
1
1
ZTM0
0
1
0
1
Zero crossing timeout period @fs=48kHz
288/fs
6ms
1152/fs
24ms
2304/fs
48ms
4608/fs
96ms
Table 11. Zero crossing timeout period
Default
[Writing operation at ALC Enable]
Writing to the area over 80H (Table 17) of IPGL/R registers is ignored during ALC operation. After ALC is disabled,
the IPGA changes to the last written data by zero-crossing or time-out. In case of writing to the DATT area under 7FH
(Table 17) of IPGL/R registers, the DATT changes even if ALC is enabled.
MS0164-E-01
- 21 -
2002/08