AK5365 Datasheet, PDF (14/41 Pages) Asahi Kasei Microsystems – 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl

ASAHI KASEI
[AK5365]
OPERATION OVERVIEW
„ System Clock
MCLK (256fs/384fs/512fs), BICK (48fs∼) and LRCK (fs) clocks are required in slave mode. The LRCK clock input must
be synchronized with MCLK, however the phase is not critical. MCLK frequency is automatically detected in slave mode.
Table 1 shows the relationship of typical sampling frequency and the system clock frequency.
MCLK (256fs/384fs/512fs) is required in master mode. MCLK frequency is selected by CKS1-0 bits as shown in Table 2.
In master mode, after setting CKS1-0 bits, there is a possibility the frequency and duty of LRCK and BICK outputs become
an abnormal state.
All external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L” and PWN bit = “1”. If these clocks
are not provided, the AK5365 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK5365 in power-down mode (PDN pin = “L” or PWN bit = “0”). In master mode, the
master clock (MCLK) must be provided unless PDN pin = “L”.
fs
32kHz
44.1kHz
48kHz
96kHz
MCLK
256fs
384fs
512fs
8.192MHz
12.288MHz
16.384MHz
11.2896MHz
16.9344MHz
22.5792MHz
12.288MHz
18.432MHz
24.576MHz
24.576MHz
N/A
N/A
Table 1. System clock example (Slave mode)
CKS1
0
0
1
1
CKS0
MCLK
32kHz ≤ fs ≤ 48kHz 48kHz < fs ≤ 96kHz
0
256fs
256fs
1
512fs
N/A
0
384fs
N/A
1
N/A
N/A
Table 2. Master clock frequency select (Master mode)
Default
„ Audio Interface Format
Two kinds of data formats can be chosen with the DIF bit (Table 3) and the CTRL pin (Table 4). The DIF bit and CTRL pin
are ORed between pin and register. In both modes, the serial data is in MSB first, 2’s compliment format. The SDTO is
clocked out on the falling edge of BICK. The audio interface supports both master and slave modes. In master mode, BICK
and LRCK are output with the BICK frequency fixed to 64fs and the LRCK frequency fixed to 1fs.
Mode
0
1
DIF bit
SDTO
LRCK BICK Figure
0
24bit, MSB justified
H/L
≥ 48fs Figure 1
1
24bit, I²S Compatible L/H
≥ 48fs Figure 2
Table 3. Audio Interface Format (CTRL pin = “L”)
Default
Mode
0
1
CTRL pin
SDTO
LRCK BICK
L
24bit, MSB justified
H/L
≥ 48fs
H
24bit, I²S Compatible L/H
≥ 48fs
Table 4. Audio Interface Format (DIF bit = “0”)
Figure
Figure 1
Figure 2
MS0164-E-01
- 14 -
2002/08