AK5365 Datasheet, PDF (10/41 Pages) Asahi Kasei Microsystems – 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl

ASAHI KASEI
Parameter
Symbol
min
typ
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
CSN “↓” to CCLK “↑”
tCSS
50
CCLK “↑” to CSN “↑”
tCSH
50
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
4.7
Start Condition Hold Time (prior to first clock pulse) tHD:STA
4.0
Clock Low Time
tLOW
4.7
Clock High Time
tHIGH
4.0
Setup Time for Repeated Start Condition
tSU:STA
4.7
SDA Hold Time from SCL Falling
(Note 17) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT 0.25
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
4.0
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Reset Timing
PDN Pulse Width
PDN “↑” to SDTO valid
PWN “↑” to SDTO valid
(Note 18)
(Note 19)
(Note 20)
tPD
150
tPDV
516
tPDV
516
Note 17. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 18. The AK5365 can be reset by bringing the PDN pin = “L”.
Note 19. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Note 20. This cycle is the number of LRCK rising edges from the PWN bit = “1”.
[AK5365]
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
100
kHz
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
1.0
µs
0.3
µs
-
µs
50
ns
ns
1/fs
1/fs
Purchase of Asahi Kasei Microsystems Co., Ltd I²C components conveys a license under the Philips I²C
patent to use the components in the I²C system, provided the system conform to the I²C specifications
defined by Philips.
MS0164-E-01
- 10 -
2002/08