AK5365 Datasheet, PDF (25/41 Pages) Asahi Kasei Microsystems – 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl

ASAHI KASEI
[AK5365]
[4] Example of ALC Operation
The following registers should not be changed during the ALC operation.
• LTM1-0, LMTH, LMAT, WTM1-0, ZTM1-0, RATT, REF7-0, ZELMN bits
• The IPGA value of Lch becomes the start value if the IPGA value is different with Lch and Rch when the ALC starts.
• Writing to the area over 80H (Table 17) of IPGL/R registers is ignored during ALC operation. After ALC is disabled,
the IPGA changes to the last written data by zero-crossing or time-out. In case of writing to the DATT area under 7FH
(Table 17) of IPGL/R registers, the DATT changes even if ALC is enabled.
Manual Mode
Set (SEL2-0 bits or SEL2-0 pins)
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (LMAT, RATT, LMTH)
WR (REF7-0)
WR (IPGA7-0)
(1)
WR (ALC = “1”)
(2)
ALC Operation
No
Finish ALC mode?
(1)
Yes
WR (ALC = “0”)
(2)
Finish ALC mode and return to manual mode
Note : WR : Write
Figure 12. Registers set-up sequence at ALC operation
(1): Enable soft mute (2): Disable soft mute
Note : ALC operation is enabled by the ALC pin.
Note : All the bits about ALC operation operate by the default value when an ALC operation is started with the ALC pin
without setting up a bit about ALC operation with the register. A bit about ALC operation operate by the setting
value when a bit about ALC operation is set up with the register and an ALC operation is started with the ALC pin.
Note : After ALC operation is disabled, the IPGA changes to the last written data during or before ALC operation.
MS0164-E-01
- 25 -
2002/08