AK5365 Datasheet, PDF (32/41 Pages) Asahi Kasei Microsystems – 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl

ASAHI KASEI
[AK5365]
„ Register Definitions
Addr Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H Power Down & Reset Control 0
0
0
0
0
0
0
PWN
Default
0
0
0
0
0
0
0
1
PWN:
Power down control
0 : Power down. All registers are not initialized.
1 : Normal Operation (Default)
“0” powers down all sections and then both IPGA and ADC do not operate. The contents of all register
are not initialized and enabled to write to the registers.
When MCLK and LRCK are changed, it is not necessary to reset by the PDN pin or PWN bit because the
AK5365 builds in reset-free circuit. However, it can be reduced the noise by reset.
Addr
01H
Register Name
Input Selector Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
SEL2 SEL1 SEL0
0
0
0
0
0
0
0
0
SEL2-0: Input selector (see Table 6)
Initial values are “000”.
Addr
02H
Register Name
Clock & Format Control
Default
D7
D6
D5
D4
D3
D2
0
0
0
0
DIF
CKS1
0
0
0
0
0
0
SMUTE: Soft Mute control
0 : Normal Operation (Default)
1 : SDTO outputs soft-muted.
CKS1-0: Master clock frequency select (see Table 2)
Initial values are “00”.
DIF: Audio interface format (see Table 3)
Initial values are “0”.
When CTRL pin is “H”, audio interface format is fixed to I²S compatible.
D1
CKS0
0
D0
SMUTE
0
MS0164-E-01
- 32 -
2002/08