AK5365 Datasheet, PDF (34/41 Pages) Asahi Kasei Microsystems – 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl

ASAHI KASEI
[AK5365]
Addr
04H
05H
Register Name
Lch IPGA Control
Rch IPGA Control
Default
D7
IPGL7
IPGR7
0
D6
IPGL6
IPGR6
1
D5
IPGL5
IPGR5
1
D4
IPGL4
IPGR4
1
D3
IPGL3
IPGR3
1
D2
IPGL2
IPGR2
1
D1
IPGL1
IPGR1
1
D0
IPGL0
IPGR0
1
IPGL/R7-0: Input PGA & Digital volume control (see Table 17)
Initial values are “7FH”.
Digital ATT with 128 levels operates when writing data of less than 7FH. This ATT is a linear ATT with 8032
levels internally and these levels are assigned to pseudo-log data with 128 levels. The transition between ATT
values has 8032 levels and is done by soft changes. For example, when ATT changes from 7FH to 7EH, the
internal ATT value decreases from 8031 to 7775, one by one every fs cycle. It takes 8031 cycles
(167ms@fs=48kHz) from 7FH to 00H (Mute).
The IPGAs are set to “00H” when PDN pin goes “L”. After returning to “H”, the IPGAs fade into the initial value,
“7FH” in 8031 cycles.
The IPGAs are set to “00H” when PWN bit goes “0”. After returning to “1”, the IPGAs fade into the current value.
The ADC output is “0” during the first 516LRCK cycles.
Writing to the area over 80H (Table 17) of IPGL/R registers is ignored during ALC operation. After ALC is
disabled, the IPGA changes to the last written data by zero-crossing or time-out. In case of writing to the DATT
area under 7FH (Table 17) of IPGL/R registers, the DATT changes even if ALC is enabled.
MS0164-E-01
- 34 -
2002/08