AK5365 Datasheet, PDF (16/41 Pages) Asahi Kasei Microsystems – 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl

ASAHI KASEI
[AK5365]
„ Power-up/down
The AK5365 is placed in the power-down mode by bringing PDN pin = “L” and the digital filter is also reset at the same
time. This reset should always be done after power-up. An analog initialization cycle starts after exiting the power-down
mode. Therefore, the output data SDTO becomes available after 516 cycles of LRCK.
(1) Power-up Sequence 1
Power Supply
(1)
PDN pin
ADC Internal State
PDN INITA
Normal
IPGA
00H 00H → 7FH
7FH
SDTO
External clocks
in slave mode
External clocks
in master mode
BICK, LRCK
in master mode
“0”
FI
Output
MCLK, LRCK, BICK
The clocks can be stopped.
MCLK
The clocks can be stopped.
Fixed to “L”
BICK, LRCK
- INITA : Initializing period of ADC analog section (516/fs).
- FI : Fade in. After exiting power down, IPGA value fades in.
- PDN : Power down state.
- The period of (1) should be min. 150ns in Figure 3.
Figure 3. Power-up Sequence 1
MS0164-E-01
- 16 -
2002/08