AK5365 Datasheet, PDF (36/41 Pages) Asahi Kasei Microsystems – 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl

ASAHI KASEI
[AK5365]
Addr Register Name
D7
06H ALC Mode Control 1
0
Default
0
D6
D5
D4
D3
D2
D1
D0
0 ZELMN ALC
FR
LMTH RATT LMAT
0
1
0
1
0
0
0
LMAT: ALC Limiter ATT step (see Table 18)
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level set by LMTH
bit, the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA value
is 94H and the LMAT bit = “1”, the IPGA transition to 92H when the ALC limiter operation starts, resulting in the
input signal level being attenuated by 1dB (=0.5dB x 2).
LMAT ATT Step
0
1
Default
1
2
Table 18. ALC limiter ATT step
RATT: ALC Recovery gain step (see Table 19)
During the ALC recovery operation, the number of steps changed from the current IPGA value is set. For example,
when the current IPGA value is 82H and RATT bit = “1” is set, the IPGA changes to 84H by the ALC recovery
operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value exceeds the
reference level (REF7-0 bits), the IPGA value does not increase.
RATT Gain Step
0
1
Default
1
2
Table 19. ALC recovery gain step
LMTH: ALC Limiter detection level / Recovery waiting counter reset level (see Table 20)
The ALC limiter detection level and the ALC recovery counter reset level may be offset by about ±2dB.
LMTH
0
1
ALC Limiter Detection Level ALC Recovery Waiting Counter Reset Level
ALC Output ≥ −0.5dBFS
−0.5dBFS > ALC Output ≥ −2.5dBFS
ALC Output ≥ −2.0dBFS
−2.0dBFS > ALC Output ≥ −4.0dBFS
Table 20. ALC Limiter detection level / Recovery waiting counter reset level
Default
FR: ALC fast recovery
0 : Disable
1 : Enable (Default)
When the impulse noise is input, the ALC recovery operation becomes faster than a normal recovery operation.
ALC: ALC enable flag
0 : ALC Disable (Default)
1 : ALC Enable
ZELMN: Zero crossing enable flag at ALC limiter operation
0 : Enable
1 : Disable (Default)
When the ZELMN bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently. The
zero crossing timeout is the same as the ALC recovery operation. When the ZELMN bit = “1”, the IPGA value is
changed immediately. The ALC Limiter period can be set up by a ZTM 1-0 bits when ZELMN bit = “0”, it can be
set up by a LTM1-0 bits when ZELMN bit = “1”
MS0164-E-01
- 36 -
2002/08