AK5365 Datasheet, PDF (31/41 Pages) Asahi Kasei Microsystems – 24-BIT 96KHZ ADC WITH SELETOR/PGA/ALCl

ASAHI KASEI
[AK5365]
„ Control by Pin and Bit
Function
ALC
Input Selector
Soft Mute
Audio Interface Format
Pin
ALC Enable Pin
(Internal Pull-down)
“L” : Disable
“H” : Enable
SEL2-0 Pin
“LLL” : LIN1/RIN1
“LLH” : LIN2/RIN2
“LHL” : LIN3/RIN3
“LHH” : LIN4/RIN4
“HLL” : LIN5/RIN5
SMUTE Pin
(Internal Pull-down)
“L” : Normal operation
“H” : Soft muted
CTRL Pin
“L” : 24bit MSB justified
“H” : 24bit I²S Compatible
Table 13. Pin and Bit control
bit
ALC Enable bit
“0” : Disable
“1” : Enable
SEL2-0 bit
“000” : LIN1/RIN1
“001” : LIN2/RIN2
“010” : LIN3/RIN3
“011” : LIN4/RIN4
“100” : LIN5/RIN5
SMUTE bit
“0” : Normal operation
“1” : Soft muted
DIF bit
“0” : 24bit MSB justified
“1” : 24bit I²S Compatible
Note : The SEL2-0 pins should be fixed to “LLL” if the AK5365 is controlled by the SEL2-0 bits, because the setting of the
SEL2-0 pins are prior to the SEL2-0 bits setting. Other Functions are ORed between pin and register.
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
Register Name
Power Down & Reset Control
Input Selector Control
Clock & Format Control
Timer Select
Lch IPGA Control
Rch IPGA Control
ALC Mode Control 1
ALC Mode Control 2
D7
0
0
0
0
IPGL7
IPGR7
0
REF7
D6
0
0
0
0
IPGL6
IPGR6
0
REF6
D5
0
0
0
LTM1
IPGL5
IPGR5
ZELMN
REF5
D4
0
0
0
LTM0
IPGL4
IPGR4
ALC
REF4
D3
0
0
DIF
ZTM1
IPGL3
IPGR3
FR
REF3
D2
0
SEL2
CKS1
ZTM0
IPGL2
IPGR2
LMTH
REF2
D1
0
SEL1
CKS0
WTM1
IPGL1
IPGR1
RATT
REF1
D0
PWN
SEL0
SMUTE
WTM0
IPGL0
IPGR0
LMAT
REF0
PDN pin = “L” resets the registers to their default values.
Note: Unused bits must contain a “0” value.
Note: Only write to address 00H to 07H.
MS0164-E-01
- 31 -
2002/08