P0103 Datasheet, PDF (36/50 Pages) AEL Crystals Ltd – Introduction of the VEEK-MT

and read ports also with 16-bit data width each. The writing clock is the same as CMOS sensor pix
clock, and the reading clock is provided by the LCD Controller, which is 33MHz.
Finally, the LCD controller fetches the RGB data from the buffer and displays it on the LCD panel
continuously. Because the resolution and timing of the LCD is compatible with WVGA@800*480,
the LCD controller generates the same timing and the frame rate can achieve about 25 fps.
For the objective of a better visual effect, the CMOS sensor is configured to enable the left right
mirror mode. User could disable this functionality by modifying the related register value being
written to CMOS controller chip.
Figure 4-12 Block diagram of the digital camera design
 Demonstration Source Code
 Project directory: Camera
 Bit stream used: Camera.sof
 Demonstration Batch File
Demo Batch File Folder: Camera\demo_batch
The demo batch file includes the following files:
 Batch File: test.bat
 FPGA Configure File: Camera.sof
VEEK-MT User Manual
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May 20, 2014