P0103 Datasheet, PDF (35/50 Pages) AEL Crystals Ltd – Introduction of the VEEK-MT

Figure 4-11 Setup for the VIP demonstration
4.6 Camera Application
This demonstration shows a digital camera reference design using the 5-Megapixel CMOS sensor
and 8-inch LCD modules on the VEEK-MT. The CMOS sensor module sends the raw image data to
FPGA on the DE2-115 board, the FPGA on the board handles image processing part and converts
the data to RGB format to display on the LCD module. The I2C Sensor Configuration module is
used to configure the CMOS sensor module. Figure 4-12 shows the block diagram of the
demonstration.
As soon as the configuration code is downloaded into the FPGA, the I2C Sensor Configuration
block will initial the CMOS sensor via I2C interface. The CMOS sensor is configured as follow:
 Row and Column Size: 800 * 480
 Exposure time: Adjustable
 Pix clock: MCLK*2 = 25*2 = 50MHz
 Readout modes: Binning
 Mirror mode: Line mirrored
According to the settings, we can calculate the CMOS sensor output frame rate is about 44.4 fps.
After the configuration, The CMOS sensor starts to capture and output image data streams, the
CMOS sensor Capture block extracts the valid pix data streams based on the synchronous signals
from the CMOS sensor. The data streams are generated in Bayer Color Pattern format. So it’s then
converted to RGB data streams by the RAW2RGB block.
After that, the Multi-Port SDRAM Controller acquires and writes the RGB data streams to the
SDRAM which performs as a frame buffer. The Multi-Port SDRAM Controller has two write ports
VEEK-MT User Manual
32
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May 20, 2014