P0103 Datasheet, PDF (32/50 Pages) AEL Crystals Ltd – Introduction of the VEEK-MT

Clocked Video
Input/Output
devices.
These two cores convert the industry-standard clocked video format (BT-656) to
Avalon-ST video and vice versa.
These functions allow you to fully integrate common video functions with video interfaces,
processors, and external memory controllers. The example design uses an Altera Cyclone® IV E
EP4CE115F29 featured VEEK-MT.
A video source is input through an analog composite port on VEEK-MT which generates a digital
output in ITU BT656 format. A number of common video functions are performed on this input
stream in the FPGA. These functions include clipping, chroma resampling, motion adaptive
deinterlacing, color space conversion, picture-in-picture mixing, and polyphase scaling.
The input and output video interfaces on the VEEK-MT are configured and initialized by software
running on a Nios® II processor. Nios II software demonstrates how to control the clocked video
input, clocked video output, and mixer functions at run-time is also provided. The video system is
implemented using the QSYS system level design tool. This abstracted design tool provides an easy
path to system integration of the video processing data path with a NTSC or PAL video input, VGA
output, Nios II processor for configuration and control. The Video and Image Processing Suite
MegaCore functions have common open Avalon-ST data interfaces and Avalon Memory-Mapped
(Avalon-MM) control interfaces to facilitate connection of a chain of video functions and video
system modeling. In addition, video data is transmitted between the Video and Image Processing
Suite functions using the Avalon-ST Video protocol, which facilitates building run-time controllable
systems and error recovery.
Figure 4-9 shows the Video and Image Processing block diagram.
VEEK-MT User Manual
29
www.terasic.com
May 20, 2014