P0103 Datasheet, PDF (14/50 Pages) AEL Crystals Ltd – Introduction of the VEEK-MT

Figure 3-1 JTAG Chain
Figure 3-2 JTAG Chain Configuration Header
 Configuring the FPGA in JTAG Mode
Figure 3-3 illustrates the JTAG configuration setup. To download a configuration bit stream into
the Cyclone IV E FPGA, perform the following steps:
 Ensure that power is applied to the VEEK-MT
 Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW19) to
the RUN position (See Figure 3-4)
 Connect the supplied USB cable to the USB-Blaster port on the VEEK-MT
 The FPGA can now be programmed by using the Quartus II Programmer module to select a
configuration bit stream file with the .sof filename extension
VEEK-MT User Manual
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May 20, 2014